The present invention relates to semiconductor devices and their fabrication methods and, more particularly, to improvement in resistance to soft errors in an ultra-small insulated gate field-effect transistor.
The performance of an insulated gate field-effect transistor (hereinbelow referred to as MOSFET) as a component of an integrated circuit device of a very high packing density has been being increased by reduction in structural dimensions in accordance with the scaling law. Specifically, as the size of the structure is reduced, a mutual conductance gm indicative of the amplification factor of the MOSFET increases and higher-density integration is realized at the same time. The scaling law contributes to even decrease in a power voltage and promotes higher-speed operation, higher packing density, and lower power operation at the same time.
FIG. 1 is a schematic diagram showing a cross section of a representative configuration example of a conventional ultra-small MOSFET. Shown in FIG. 1 are a semiconductor substrate 1, a deep source/drain diffusion layer 2, a shallow source/drain diffusion layer (called an extension) 3, a locally high-density doping region 5 also called a pocket, a gate insulating film 6, a gate electrode 7, a gate side wall insulating film 8, a silicide film 9, a surface passivation insulating film 10, and a source/drain electrode 11. The diagram shows an example of an ultra-small MOS having a double diffusion structure for realizing a source/drain of a low-resistance and a shallow junction.
As the MOS structure is decreasing in size, a kind of conduction phenomenon called punch-through appears between the source and drain and it is a factor of preventing the MOS structure from decreasing in size. As means for solving the problem, developments for a shallower source/drain junction and the locally high-density doping technique of a channel region have been being promoted.
On the other hand, as shown in FIG. 2A, as a technique maximally utilizing the performance of a MOSFET and realizing a higher-performance function, a complementary circuit configuration (complementary-MOSFET: CMOS) in which an n conduction type MOSFET (nMOS) and a p conduction type MOSFET (pMOS) are connected in series has been proposed and is widely used. A flip flop formed by combining two complementary circuits is widely used as a memory device (static random access memory, hereinbelow, abbreviated as SRAM) FIG. 2B shows the circuit configuration of the SRAM.
Because of its configuration of the bistable circuit, it is said that the SRAM is stable against an unexpected disturbance and noise from the outside. In recent years, however, a lower voltage is used for reduction in power consumption and an erroneous operation due to an external disturbance, particularly, high-energy rays emitted irregularly from outer space is sometimes recognized. For example, as shown by the arrow in the SRAM of FIG. 2B, the SRAM is irradiated with alpha-particles, so that an output of the CMOS is shifted to a low potential although for extremely short time, causing inversion of data stored in the SRAM or the like. One of methods of preventing the phenomenon is a method of adding a capacitance which absorbs occurrence of an abnormal voltage. To be specific, as shown in FIG. 2C, a tank (capacitor) for temporarily storing electrons or holes generated by the irradiation of alpha particles is provided. By adding a capacitance Ca on the output side of a CMOS, a potential drop can be prevented. However, there is a problem that the operation speed of the whole SRAM is decreased.
FIG. 3 shows a result of analysis by device simulation, of changes in outputs in the case where the capacitance Ca is added to the output side of the CMOS and the CMOS is irradiated with alpha particles. As obviously understood from comparison between the case where the additional capacitance Ca is not provided and the case where the additional capacitance Ca is provided, by the additional capacitance Ca of about 0.7 fF, shift to a lower potential due to the alpha-particles induced is suppressed. From the viewpoint of stability of the operation of the SRAM, it can be said that even reduction of such a degree produces an effect. To be more reliable, the additional capacitance Ca of about 1.8 fF is effective. As described above, by adding the capacitance on the output side of the CMOS, it is understood that a drop in the potential can be prevented and resistance to alpha particles can be improved. However, the method has a problem that the operation speed of the whole SRAM deteriorates.
Methods of preventing a generated electron-hole pair from arriving at an active region of a semiconductor device by making a layer-state breakwater are disclosed in Japanese Unexamined Patent Application Nos. 59-84461 and 59-94451. According to the methods, a high-density impurity region serving as a breakwater is formed so as to have a layer structure (hereinbelow, called a layer-shaped breakwater) in a lower region of the active region. In the former method, a high-density doped layer serving as a layer-shaped breakwater is formed so, as not to be in contact with a source/drain region of high density. In the latter method, the high-density doped layer is formed so as to be in contact with the source/drain region of high density. Whether the high-density doped layer is in contact or not exerts an influence on a capacitance value in a semiconductor device but the effect of a soft error protection is the same.
Cosmic rays incident from the outside of a semiconductor device have no regularity and no order in the incident direction and position so that generation of an electron-hole pair by irradiation of high-energy rays cannot be prevented. That is, when a semiconductor device is irradiated with cosmic rays, exposure positions in the semiconductor device completely have no order. Therefore, whether the high-energy rays pass through the center portion from right above as in the known techniques or the peripheral portion of a MOS cannot be specified. When the rays pass through the center portion from right above, the conventional layer-shaped breakwater effectively acts. However, when the rays pass through the peripheral portion, the flow of electrons and holes generated in association with the exposure in a well is not blocked by the layer-shaped breakwater but the electrons and holes easily reach the active region of the MOS. That is, the layer-shaped breakwater cannot always sufficiently deal with occurrence of a soft error.
The cosmic rays that cause a soft error are a natural phenomenon and cannot be prevented from being generated. Consequently, it is desired to prevent irradiation of high-energy rays. However, some cosmic rays such as neutron rays penetrate even one meter of concrete, so that it is unrealistic to completely block the cosmic rays. It is therefore necessary to take some countermeasure for the semiconductor itself. As described above, the structure including the layer-shaped breakwater for preventing the electrons and holes generated at the time of exposure to high-energy rays from being diffused to the active region is known by Japanese Unexamined Patent Application Nos. 59-84461 and 59-94451 and the like.
However, it is troublesome that the incident directions and positions of cosmic rays that cause a soft error do not have regularity. When the center portion of the MOS is exposed to the high-energy rays, the layer-shaped breakwater can effectively plays its role but when the high-energy rays are incident on the peripheral portion, as described above, a problem arises such that the flow of the electrons and holes cannot be effectively blocked.
An object of the invention is to provide a semiconductor device having high resistance to a soft error which is caused by high-energy rays from outer space and high-performance driving capability.
To more specifically describe an erroneous operation caused by cosmic rays, particularly, alpha particles and a pn junction as a basic configuration of the invention, FIG. 4 schematically shows a state where a pn junction is irradiated with alpha particles. Shown in FIG. 4 are a region 1 of a first conduction type, an impurity region 2 of a second conduction type in which impurity is diffused deep at high density, and an impurity region 3 of the second conduction type in which impurity is diffused shallow. A pn junction is formed between the region 1 of the first conduction type and the impurity region 2 of the second conduction type of high density and deep diffusion, and a pn junction is formed between the region 1 of the first conduction type and the impurity region 3 of shallow diffusion. According to the invention, in such a structure, an impurity region 4 of the fist conduction type of higher density than the impurity density of the region 1 of the first conduction type is provided between the region 1 of the first conduction type and the region 2 of the second conduction type. The thickness of the impurity region 4 of the first conduction type is suppressed so as not to cover the impurity region 3 of the second conduction type of shallow diffusion. In such a manner, the width of a depletion layer formed between the region 1 of the first conduction type and the region 2 of the second conduction type can be set to be narrow and uniform.
In the case where a semiconductor device is irradiated with alpha particles, the energy is dissipated and it newly generates an electron-hole pair in the semiconductor. The generated electron-hole pair in an initial state is electrically neutral from a macroscopic viewpoint. With a lapse of time, electrons and holes are diffused into the semiconductor (usually, diffused in opposite directions) and cause an abnormal potential in the semiconductor. When the abnormal potential is smaller than a power source voltage, there is no problem. However, as described above, when the power source voltage is decreased for reduction in power and the abnormal potential becomes unignorable, the abnormal potential becomes a factor of causing erroneous operation.
When the electrons and holes generated by the exposure of high-energy rays exist in the electrically neutral range of the semiconductor device, the electrons and holes are recombined with time and a large influence is not exerted on the operation. In contrast, when the irradiation position is in the depletion layer as the electrically neutral region, the generated electrons and holes exert an adverse influence on the device operation. Thus, although the irradiation position cannot be controlled, as a countermeasure, the width of the depletion layer formed near the pn junction can be narrowed.
The position of exposure in the semiconductor device, that is, an exposure ratio is proportional to the area ratio in statistics. With respect to the peripheral portion, the width of the depletion layer is multiplied with the length of the peripheral portion to calculate a substantial exposure area. In the case of the micro-structure MOS, for example, when impurity atoms are ion-implanted from a diffusion window whose one side is 0.14 micron to thereby form a pn junction for forming the source/drain areas, the plane area of the pn junction is 0.0196 square micron. In contrast, when it is assumed that the width of the depletion layer is 0.1 micron, the area formed by the depletion layer in the peripheral portion is 0.056 square micron. That is, in the case of the latest micro junction, the area ratio between the center portion and the peripheral portion is about 1:3, and the area of the peripheral portion is larger. Consequently, the conventional layer-shaped breakwater cannot sufficiently deal with exposure in the peripheral portion and occurrence of soft errors. Therefore, a technique of effectively enhancing resistance also to high energy rays incident from any directions and positions is necessary.
It can be generally said that when a high-density region is formed so as to surround the pn junction, the width of the depletion layer can be uniformly reduced. In the case of a vertical structure MOSFET, such a structure can be designed so that the operation of a MOS can be performed. In a horizontally-long MOSFET, the region between the source and the drain becomes a high-density region of an opposite conduction type. Consequently, the threshold of the MOSFET becomes remarkably high, and it is unpreferable for designing of a higher-performance MOSFET. To be specific, when the operation voltage is decreased in accordance with the trend of a lower voltage, to maintain the drain current and mutual conductance at large values and to set the impurity density in the peripheral portion to be high are contradictory.